Extension Details
- Verilog
- by Tom Salvo
- 3 Recent Installs | 177 Total Installs
- Basic syntax highlighting and linting for Verilog and System Verilog
- Repository
- Bug Reports
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Read & Write Files
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Launch Subprocesses
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This extension is allowed to:
Readme
Verilog provides basic (and likely incomplete) syntax highlighting for the Verilog (.v or .V files) or System Verilog (.sv or .SV files) languages.
It can also be used as a linter for your source files if you have Verilator installed on your machine. An easy way to do this is via homebrew and typing the command brew install verilator.
Release Notes
Version 0.0.7
- update repo and issues URLs to codeberg
Version 0.0.6
- Added supporf for System Verilog header (.svh) files
- Added support for missing System Verilog variable types
- Added support for ifndef and endif
- Added support for System Verilog macro keyword
- Added clog2 keyword
Version 0.0.4
- Fixed an issue where
xandzvariable names would highlight incorrectly as values
Version 0.0.3
- Added some missing symbol names (
logic,always_comb,always_ff) (thanks DidierMalenfant) - Verilator linting: Only create issues for the current file. (thanks DidierMalenfant)
Version 0.0.2
- Added System Verilog to the supported extensions. (thanks DidierMalenfant)
- Added basic linting support using verilator. (thanks DidierMalenfant)
Version 0.0.1
- Initial release