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    Extension Details



    Readme

    SystemVerilog provides syntax highlighting and autocompletion for Verilog, SystemVerilog, UVM.

    Language Support

    SystemVerilog currently supports the following features of V/SV/UVM Language:

    • Comments
    • extension detector

    Support for:

    • Syntaxes highlight

    is planned for a future update.

    Release Notes

    Version 1.0

    Initial release